A ”Dual clock FIFO synchronizer” is a register buffer where data is inserted from the write clock domain and data is removed from the read clock domain. Since both work within their own respective clock domains, using a dual-port buffer, such as a FIFO, is a safe way to pass multi-bit values between clock domains.
Full Answer
What is a dual clock FIFO?
This dual clock FIFO is designed as a way for two circuits operating in different clock frequencies to communicate with each other. There is a read side and write side where data is stored into the internal memory of the FIFO using the write side clock and then read from the internal memory using the read side clock.
How does the FIFO synchronizer work?
The usage of the FIFO synchronizer assumes that the data rate of the read side is at least as fast as the write side, so the FIFO does not get overflowed and generate unnecessary flow control. The depth of the FIFO should assume temporal differences in the data rate and accommodate some extra entries for the purpose of buffering such effects.
What is FIFO synchronizer in Verilog RTL?
This component contains a verified Verilog RTL code of the asynchronous FIFO synchronizer with parametric data bus width. The synchronizer allows the transfer of wide vectors across clock domain with minimal timing requirements and no meta-stability issues.
What is a three-flop synchronizer used for mesochronous clock domain?
(a) Three-flop synchronizer used for mesochronous clock-domain are separated by a long link whose delay cannot fit within the target crossing and (b) example of its operation. The spread between the write and operating frequency.
How does a 2 clock FIFO work?
This dual clock FIFO is designed as a way for two circuits operating in different clock frequencies to communicate with each other. There is a read side and write side where data is stored into the internal memory of the FIFO using the write side clock and then read from the internal memory using the read side clock.
What is Async FIFO?
An asynchronous FIFO refers to a FIFO design where data values are written to a FIFO buffer from one clock domain and the data values are read from the same FIFO buffer from another clock domain, where the two clock domains are asynchronous to each other.
What is synchronous and asynchronous FIFO?
FIFO can be either synchronous or asynchronous. The basic difference between them is that the entire operation of synchronous FIFO is entirely dependent on the clock where as the write operation and read operation of asynchronous FIFO are asynchronous to each other.
What is asynchronous FIFO in Verilog?
An asynchronous FIFO refers to a FIFO where data is written from one clock domain, read from a different clock domain, and the two clocks are asynchronous to each other. Clock domain crossing logic is inherently difficult to design, and even more difficult to verify.
What is FIFO stands for?
First In First OutFIFO = First In First Out FIFO means that products stored first are to be retrieved first.
How does FIFO memory work?
FIFO means First-In First-Out. A FIFO is a structure used in hardware or software application when you need to buffer a data....Input as burst data;Output as continuous data.The FIFO is used to buffer the minimum number of burst data in order to guarantee continuous reading from FIFO without interruption.
What are asynchronous clocks?
ASYNCHRONOUS CLOCK… 11 If the two clocks are with different phase and the frequency may or may not be same then the clock is known as asynchronous signal If the source of the two clocks is different then there is chance of phase difference then it will leads to synchronous clock.
What is the difference between synchronous and asynchronous?
The key difference between synchronous and asynchronous communication is synchronous communications are scheduled, real-time interactions by phone, video, or in-person. Asynchronous communication happens on your own time and doesn't need scheduling.
Why FIFO is used in digital electronics?
FIFOs are commonly used in electronic circuits for buffering and flow control between hardware and software. In its hardware form, a FIFO primarily consists of a set of read and write pointers, storage and control logic.
What is clock domain crossing in VLSI?
In digital electronic design a clock domain crossing (CDC), or simply clock crossing, is the traversal of a signal in a synchronous digital circuit from one clock domain into another. If a signal does not assert long enough and is not registered, it may appear asynchronous on the incoming clock boundary.
How do you create a FIFO?
4:539:04So in the beginning a five-four is empty. The 5 who is empty. Both right pointer and read pointer.MoreSo in the beginning a five-four is empty. The 5 who is empty. Both right pointer and read pointer. Then this pointers will be pointed to 0. This are just for the reference.
How do you calculate asynchronous FIFO depth?
Example : FIFO Depth Calculation If if we have alternate read cycles i.e between two read cycle there is IDLE cycle. If 10 IDLE cycles betweeen two read cycles . FIFO DEPTH = B - B *F2/(F1*10) .
Description
This dual clock FIFO is designed as a way for two circuits operating in different clock frequencies to communicate with each other. There is a read side and write side where data is stored into the internal memory of the FIFO using the write side clock and then read from the internal memory using the read side clock.
Documentation
For additional information and/or suggestions email: astillmaker -a,t- ucdavis -period- edu
What is asynchronous synchronizer?
Asynchronous FIFO synchronizer offers a solution for transferring signals and vectors across clock domains without risking meta-stability and coherency problems resulting from partial vector synchronization. The synchronizer is suitable for synchronization of data and control information between asynchronous domain of known data and clock ratio. This component contains a verified Verilog RTL code of the asynchronous FIFO synchronizer with parametric data bus width. The synchronizer allows the transfer of wide vectors across clock domain with minimal timing requirements and no meta-stability issues. The synchronizer uses a FIFO with one clock domain for load and another clock domain for extract. Data is written into the FIFO at one clock domain, and only later is read from the FIFO in the other clock domain. The FIFO itself can be implemented using an embedded memory or an array of registers.
Why use grey code in synchronizer?
The synchronizer uses Grey code to prevent meta stability between the two clock domains. The pointer on the write side is encoded from binary to Grey code and that goes through a full synchronizer, and then translated again into binary on the read side. The synchronized write pointer is than compared to the read pointer to generate the empty signal used for flow controlling the FIFO extract side. As the comparison between the changed write pointer and the read pointer is inevitably later than the actual load of data to the memory array, the FIFO depth should be able to absorb further loads happening during that delay time. For more details about the Grey code and its advantages for clock domain crossing refer to the decoders section here.
How does a read pointer synchronization work?
The read pointer synchronization uses a Grey code encoding to overcome the uncertainties of clock domain crossing and prevent unexpected read pointer values at the write clock domain. The read pointer is encoded into Grey code, goes through a full synchronizer and then decoded back into binary, to be compared with the write pointer to generate the full indication. the full indication is used for flow control of the loaded data. The comparison is late, compared to the actual read operation, so more entries may be extracted during that time. The FIFO depth needs to accommodate this delay in order to prevent unnecessary bubbles on the read side.
What happens when a signal is passed between two clock domains?
If a signal is passed between two clock domains then there is a chance that the signal could go meta stable, i.e a state where the signal is has not settled to either a high or low (1 or 0). In FPGA latching a meta-stable signal can cause entire designs to come to halt.
What is CDC in synchronization?
For multi bit clock domain crossing (CDC) using m-FF synchronizer, it is preferable to grey encode the control data. This is because, CDC only ensures that you are latching a stable signal at the destination clock domain, it does not ensure that you are latching the correct data.
Why are clocks in the same domain?
For example, a clock and its derived clock (via a BUFR, Divider) are in the same clock domain because they have a constant phase relationship. But, 100MHz and 59MHz clocks (whose phase relationship changes over time) are in two separate clock domains.
What is a two flip flop synchronizer?
In general, a conventional two flip-flop synchronizer is used for synchronizing a single bit level signal. As shown in Figure 1 and Figure 2 , flip flop A and B1 are operating in asynchronous clock domain. There is probability that while sampling the input B1-d by flip flop B1 in CLK_B clock domain, output B1-q may go into metastable state. But during the one clock cycle period of CLK_B clock, output B1-q may settle to some stable value. Output of flop B2 can go to metastable if B1 does not settle to stable value during one clock cycle, but probability for B2 to be metastable for a complete destination clock cycle is very close to zero.
What is request and acknowledge mechanism?
In this synchronization scheme request and acknowledge mechanism is used to guarantee the sampling of correct data into destination clock domain irrespective of clock ratio between source clock and destination clock. This technique is mainly used to synchronize vector signal which is not changing continuously or very frequently. As shown in Figure 12 , data should remain stable on the bus until synchronized Acknowledge signal (A2-q) is received from destination side and it (A2-q) goes low. Diagram in Figure 11 shows this implementation and Figure 12 shows timing for handshake synchronizer.
What is a synchronizer?
A synchronizer is a circuit whose purpose is to minimize the probability of a synchronization failure. We want the metastability to resolve within a synchronization period (a period of the destination clock) so that we can safely sample the output of the flip-flop in the destination clock domain.
What is a flip flop synchronizer?
The most basic synchronizer is two flip-flop in series, both clocked by the destination clock. This simple and unassuming circuit is called a two flip-flop synchronizer. If the input data changes very close to the receiving clock edge (within setup/hold time), the first flip-flop in the synchronizer may go metastable, but there is still a full clock for the signal to become stable before being sampled by the second flip-flop. The destination domain logic then uses the output from the second flip-flop. Theoretically it is possible for the signal to still be metastable by the time it is clocked into the second flip-flop (every MTBF years). In that case a synchronization failure occurs and the design would likely malfunction.
Can a pulse disappear before being sampled by a slow clock?
The obvious problem is if a pulse on the fast signal is shorter than the period of the slow clock, then the pulse can disappear before being sampled by the slow clock. This scenario is shown in the waveform below.
Synchronizing Pointers Across Clock Domains
- Synchronizing a binary count (pointer) across clock domains is going to pose a difficulty, however. All bits of a binary counter can change simultaneously, for example a 4-bit count changing from 7->8 (4’b0111->4’b1000). To pass this value safely across a clock domain crossin…
Gray Code Counter
- The Gray code counter used in this design is “Style #2” as described in Cliff Cumming’s paper. The FIFO counter consists of an n-bit binary counter, of which bits [n-2:0] are used to address the FIFO memory, and an n-bit Gray code register for storing the Gray count value to synchronize to the opposite clock domain. One important aspect about a Gray code counter is they generally must …
Constraining Timing of The Gray Code Signals
- A coworker educated me that there is one more piece needed, after coding the gray code counters. Gray code solves metastability because the destination sees only 1 bit changing at any time. However, without specifying a timing constraint, it is possible for the design to be implemented as circuitry on silicon (or FPGA) such that the different bits of the gray code count…
Generating Full & Empty Conditions
- The FIFO is empty when the read pointer and the synchronized write pointer, including the extra bit, are equal. In order to efficiently register the rempty output, the synchronized write pointer is actually compared against the rgraynext (the next Gray code to be registered into rptr). The full flag is trickier to generate. Dissecting the Gray code sequence, you can come up with the followi…
Asynchronous FIFO (Style #1) – Putting It Together
- Here is the complete asynchronous FIFO put together in a block diagram. The design is partitioned into the following modules. 1. fifo1 – top level wrapper module 2. fifomem – the FIFO memory buffer that is accessed by the write and read clock domains 3. sync_r2w – 2 flip-flop synchronizer to synchronize read pointer to write clock domain 4. sync_w2r – 2 flip-flop synchro…
Conclusion
- An asynchronous FIFO is a proven design technique to pass multi-bit data across a clock domain crossing. This article describes one known good method to design an asynchronous FIFO by synchronizing Gray code pointers across the clock domain crossing to determine full and empty conditions. Whew! This has been one of the longer articles. I’m simultaneously surprised that 1) …
References
- Simulation and Synthesis Techniques for Asynchronous FIFO Design
- Frank Gray, “Pulse Code Communication.” United States Patent Number 2,632,058. March 17, 1953
Sample Source Code
- The accompanying source code for this article is the dual-clock asynchronous FIFO design with testbench, which generates the following waveform when run. Download and run the code to see how it works!